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MC74AC273, MC74ACT273 Octal D Flip-Flop
The MC74AC273/74ACT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.
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PDIP-20 N SUFFIX CASE 738
20 1
* * * * * * * * *
Ideal Buffer for MOS Microprocessor or Memory Eight Edge-Triggered D Flip-Flops Buffered Common Clock Buffered, Asynchronous Master Reset See MC74AC377 for Clock Enable Version See MC74AC373 for Transparent Latch Version See MC74AC374 for 3-State Version Outputs Source/Sink 24 mA ACT273 Has TTL Compatible Inputs
VCC 20 Q7 19 D7 18 D6 17 Q6 16 Q5 15 D5 14 D4 13 Q4 12 CP 11
20 1
SO-20 DW SUFFIX CASE 751
20 1
TSSOP-20 DT SUFFIX CASE 948E EIAJ-20 M SUFFIX CASE 967
20 1
ORDERING INFORMATION
Device MC74AC273N MC74ACT273N MC74AC273DW Package PDIP-20 PDIP-20 SOIC-20 SOIC-20 SOIC-20 SOIC-20 TSSOP-20 Shipping 18 Units/Rail 18 Units/Rail 38 Units/Rail 1000 Tape & Reel 38 Units/Rail 1000 Tape & Reel 75 Units/Rail
1 MR
2 Q0
3 D0
4 D1
5 Q1
6 Q2
7 D2
8 D3
9 Q3
10 GND
MC74AC273DWR2 MC74ACT273DW MC74ACT273DWR2 MC74AC273DT
Figure 1. Pinout: 20-Lead Packages Conductors (Top View)
PIN ASSIGNMENT
PIN D0-D7 MR CP Q0-Q7 FUNCTION Data Inputs Master Reset Clock Pulse Input Data Outputs
MC74AC273DTR2 MC74ACT273DT MC74ACT273DTR2 MC74AC273M MC74AC273MEL MC74ACT273M MC74ACT273MEL
TSSOP-20 2500 Tape & Reel TSSOP-20 75 Units/Rail
TSSOP-20 2500 Tape & Reel EIAJ-20 EIAJ-20 EIAJ-20 EIAJ-20 40 Units/Rail 2000 Tape & Reel 40 Units/Rail 2000 Tape & Reel
DEVICE MARKING INFORMATION
See general marking information in the device marking section on page 7 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2001
1
May, 2001 - Rev. 5
Publication Order Number: MC74AC273/D
MC74AC273, MC74ACT273
MODE SELECT-FUNCTION TABLE
D0 D1 D2 D3 D4 D5 D6 D7 CP MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Inputs Operating Mode MR Reset (Clear) Load 1 Load 0 L H H CP X Dn X H L Qn L H L Outputs
Figure 2. Logic Symbol
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition
D0 CP
D1
D2
D3
D4
D5
D6
D7
D
Q CP RD
D
Q CP RD
D
Q CP RD
D
Q CP RD
D
Q CP RD
D
Q CP RD
D
Q CP RD
D
Q CP RD
MR O0 NOTE: O1 O2 O3 O4 O5 O6 O7
That this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
MAXIMUM RATINGS*
Symbol VCC VIN VOUT IIN IOUT ICC Tstg Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC VCC or GND Current per Output Pin Storage Temperature Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 20 50 50 -65 to +150 Unit V V V mA mA mA C
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
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MC74AC273, MC74ACT273
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin, Vout Supply Voltage DC Input Voltage, Output Voltage (Ref. to GND) VCC @ 3.0 V tr, tf Input Rise and Fall Time (Note 1) AC Devices except Schmitt Inputs VCC @ 4.5 V VCC @ 5.5 V tr, tf TJ TA IOH IOL In ut Input Rise and Fall Time (Note 2) ACT Devices except Schmitt Inputs Junction Temperature (PDIP) Operating Ambient Temperature Range Output Current - High Output Current - Low VCC @ 4.5 V VCC @ 5.5 V Parameter AC ACT Min 2.0 4.5 0 - - - - - - -40 - - Typ 5.0 5.0 - 150 40 25 10 8.0 - 25 - - Max 6.0 5.5 VCC - - - - ns/V - 140 85 -24 24 C C mA mA ns/V V V Unit
1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. VIN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
DC CHARACTERISTICS
74AC Symbol Parameter VCC (V) TA = +25C Typ VIH Minimum High Level u g ee Input Voltage Maximum Low Level a u o ee Input Voltage Minimum High Level u g ee Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum Low Level a u o ee Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN IOLD IOHD ICC Maximum Input a u u Leakage Current Minimum Dynamic Output C O t t Current t Maximum Quiescent a u Qu esce Supply Current 5.5 55 5.5 5.5 5.5 55 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 - - - 0.002 0.001 0.001 - - - - - - - 74AC TA = -40C to +85C Unit Conditions
Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 0.1 0 1 - - 8.0 80 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 1.0 1 0 75 -75 80 V VOUT = 0.1 V or VCC - 0.1 V VOUT = 0.1 V or VCC - 0.1 V IOUT = -50 A V *VIN = VIL or VIH -12 mA IOH -24 mA -24 mA IOUT = 50 A V *VIN = VIL or VIH 12 mA IOL 24 mA 24 mA VI = VCC, GND VOLD = 1.65 V Max VOHD = 3.85 V Min VIN = VCC or GND
VIL
V
VOH
V
V
A mA mA A
*All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time. NOTE: Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
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MC74AC273, MC74ACT273
AC CHARACTERISTICS (For Figures and Waveforms - See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC Symbol Parameter VCC* (V) Min fmax tPLH tPHL tPHL Maximum Clock Frequency Propagation Delay Clock to Output Propagation Delay Clock to Output Propagation Delay MR to Output 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 90 140 4.0 3.0 4.0 3.0 4.0 3.0 TA = +25C CL = 50 pF Typ 125 175 7.0 5.5 7.0 5.0 7.0 5.0 Max - - 12.5 9.0 13.0 10.0 13.0 10.0 74AC TA = -40C to +85C CL = 50 pF Min 75 125 3.0 2.5 3.5 2.5 3.5 2.5 Max - - 14.0 10.0 14.5 11.0 14.0 10.5 Mhz ns ns ns 3-3 3-6 3-6 3-6 Unit Fig. No.
*Voltage Range 3.3 V is 3.3 V 0.3 V. Voltage Range 5.0 V is 5.0 V 0.5 V.
AC OPERATING REQUIREMENTS
74AC Symbol Parameter VCC* (V) Typ ts th tw tw trec Setup Time, HIGH or LOW Data to CP Hold Time, HIGH or LOW Data to CP Clock Pulse Width HIGH or LOW MR Pulse Width HIGH or LOW Recovery Time MR to CP 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.5 2.5 -2.0 -1.0 3.5 2.5 2.0 1.5 1.5 1.0 TA = +25C CL = 50 pF 74AC TA = -40C to +85C CL = 50 pF Unit Fig. No.
Guaranteed Minimum 5.5 4.0 0 1.0 5.5 4.0 5.5 4.0 3.5 2.0 6.0 4.5 0 1.0 6.0 4.5 6.0 4.5 4.5 3.0 ns ns ns ns ns 3-9 3-9 3-6 3-6 3-9
*Voltage Range 3.3 V is 3.3 V 0.3 V. Voltage Range 5.0 V is 5.0 V 0.5 V.
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MC74AC273, MC74ACT273
DC CHARACTERISTICS
74ACT Symbol Parameter VCC (V) TA = +25C Typ VIH VIL VOH Minimum High Level u g ee Input Voltage Maximum Low Level a u o ee Input Voltage Minimum High Level u g ee Output Voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum Low Level a u o ee Output Voltage 4.5 5.5 4.5 5.5 IIN ICCT IOLD IOHD ICC Maximum Input a u u Leakage Current Additional Max. ICC/Input Minimum Dynamic Output C O t t Current t Maximum Quiescent a u Qu esce Supply Current 55 5.5 5.5 5.5 5.5 5.5 55 1.5 1.5 1.5 1.5 4.49 5.49 - - 0.001 0.001 - - - 0.6 - - - 74ACT TA = -40C to +85C Unit Conditions
Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0 1 0.1 - - - 8.0 80 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1 0 1.0 1.5 75 -75 80 V V V VOUT = 0.1 V or VCC - 0.1 V VOUT = 0.1 V or VCC - 0.1 V IOUT = -50 A *VIN = VIL or VIH -24 mA IOH -24 mA IOUT = 50 A *VIN = VIL or VIH 24 mA IOL 24 mA VI = VCC, GND VI = VCC - 2.1 V VOLD = 1.65 V Max VOHD = 3.85 V Min VIN = VCC or GND
V
V
V
A mA mA mA A
*All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS (For Figures and Waveforms - See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74ACT Symbol Parameter VCC* (V) Min fmax tPHL tPLH tPHL Maximum Clock Frequency Pro agation Propagation Delay Clock to Output Pro agation Propagation Delay Clock to Output Pro agation Propagation Delay MR to Output 5.0 50 5.0 50 5.0 50 5.0 50 125 3.0 30 3.0 30 3.0 30 TA = +25C CL = 50 pF Typ 200 6.0 60 6.5 65 7.0 70 Max - 10 11 11 74ACT TA = -40C to +85C CL = 50 pF Min 125 2.5 25 2.5 25 2.5 25 Max - 11.0 11 0 12.0 12 0 11.5 11 5 MHz ns ns ns 3-3 3-6 3-6 3-6 Unit Fig. No.
*Voltage Range 5.0 V is 5.0 V 0.5 V.
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MC74AC273, MC74ACT273
AC OPERATING REQUIREMENTS
74ACT Symbol Parameter VCC* (V) Typ ts th tw tw trec Setu Setup Time, HIGH or LOW Data to CP Hold Time, HIGH or LOW Data to CP Clock Pulse Width HIGH or LOW MR Pulse Width HIGH or LOW Recovery Time MR to CP 5.0 50 5.0 50 5.0 50 50 5.0 5.0 50 3.0 30 -2.5 -2 5 2.5 25 25 2.5 -1.0 -1 0 TA = +25C CL = 50 pF 74ACT TA = -40C to +85C CL = 50 pF Unit Fig. No.
Guaranteed Minimum 4.5 45 2.0 20 4.0 40 40 4.0 2.0 20 5.0 50 2.0 20 4.5 45 45 4.5 3.0 30 ns ns ns ns ns 3-9 3-9 3-6 3-6 3-6
*Voltage Range 5.0 V is 5.0 V 0.5 V.
CAPACITANCE
Symbol CIN CPD Input Capacitance Power Dissipation Capacitance Parameter Value Typ 4.5 50 Unit pF pF Test Conditions VCC = 5.0 V VCC = 5.0 V
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MC74AC273, MC74ACT273
MARKING DIAGRAMS
PDIP-20 MC74AC273N AWLYYWW SO-20 AC273 AWLYYWW TSSOP-20 EIAJ-20
AC 273 ALYW
74AC273 AWLYWW
MC74ACT273N AWLYYWW
ACT273 AWLYYWW
ACT 273 ALYW
74ACT273 AWLYWW
A WL, L YY, Y WW, W
= Assembly Location = Wafer Lot = Year = Work Week
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MC74AC273, MC74ACT273
PACKAGE DIMENSIONS
PDIP-20 N SUFFIX 20 PIN PLASTIC DIP PACKAGE CASE 738-03 ISSUE E
-A-
20 1 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
B
10
C
L
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
SO-20 DW SUFFIX 20 PIN PLASTIC SOIC PACKAGE CASE 751D-05 ISSUE F
D q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
A
11 X 45 _
H
M
B
M
20
10X
0.25
E
1
10
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
h
18X
e
A1
T
C
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L
MC74AC273, MC74ACT273
PACKAGE DIMENSIONS
TSSOP-20 DT SUFFIX 20 PIN PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE A
20X
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
2X
L/2
B L
PIN 1 IDENT 1 10
J J1
-U-
SECTION N-N 0.25 (0.010) M
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
EIAJ-20 M SUFFIX 20 PIN PLASTIC EIAJ PACKAGE CASE 967-01 ISSUE O
20
11
LE Q1 M_ L DETAIL P
E HE
1
10
Z D e VIEW P A
b 0.13 (0.005)
M
A1 0.10 (0.004)
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III III III
DETAIL E
20
11
K K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --0.81 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.032
c
MC74AC273, MC74ACT273
Notes
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MC74AC273, MC74ACT273
Notes
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MC74AC273, MC74ACT273
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MC74AC273/D

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